Closed-loop clock circuits, such as phase-locked and delay-locked loops, are useful in many applications, including clock and data recovery, data retiming, clock regeneration, and other functions. Delay-locked loops are particularly useful in high-speed systems, such as high-speed memory systems.
Delay-locked loops can generate clock signals, or they can receive clocks signals. For example, a delay-locked loop in a first circuit may generate and provide a clock signal to a delay-locked loop in a second circuit. These delay-locked loops can clean up clock signals by removing jitter and spurious noise components. They can also retime signals to improve the performance of data transfer systems.
Various parameters or attributes can be used to describe the operating characteristics of these closed-loop clock circuits such as delay-locked loops. Loop bandwidth is one such key parameter for delay-locked loops. As loop bandwidth is increased, the resulting jitter is increased, but acquisition time, the time it takes for a delay-locked loop to lock onto an incoming clock signal, is reduced. Conversely, as loop bandwidth is decreased, the resulting jitter is decreased, but the acquisition time is increased.
Thus, jitter and acquisition time can be traded off against each other, but they cannot both be optimized. That is, all things being equal, a decrease in jitter comes at the expense of an increase in acquisition time. Similarly, a decrease in acquisition time comes at the expense of an increase in jitter.
Under most circumstances, it is desirable to decrease jitter. A reduced jitter improves data recovery and reduces transmission errors. But on occasion, for example, when phase error is large, a decrease in acquisition time becomes desirable, even at the expense of increased jitter. Again, jitter and acquisition time can be varied by adjusting loop bandwidth.
Thus, what is needed are circuits, methods, and apparatus that allow the bandwidth for closed-loop clock circuits, such as phase-locked and delay-locked loops, to vary with changes in phase error.